 radeon_span.c |   81 +++++++++++++++++++++++++++++++++++++++++++++++-----------
 2 files changed, 67 insertions(+), 14 deletions(-)

diff -u xc-orig/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c
--- xc-orig/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c	2004-06-16 03:18:21.000000000 -0600
+++ xc/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c	2005-10-17 13:19:07.000000000 -0600
@@ -70,11 +70,12 @@
    radeonScreenPtr radeonScreen = rmesa->radeonScreen;			\
    __DRIscreenPrivate *sPriv = rmesa->dri.screen;			\
    __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;			\
+   GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp;         \
    GLuint height = dPriv->h;						\
    GLuint xo = dPriv->x;						\
    GLuint yo = dPriv->y;						\
    char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset);	\
-   (void) buf
+   (void) buf; (void) pitch; (void)xo; (void)yo
 
 #define LOCAL_STENCIL_VARS	LOCAL_DEPTH_VARS
 
@@ -243,6 +244,15 @@
 #define TAG(x) radeon##x##_16
 #include "depthtmp.h"
 
+#define WRITE_DEPTH(_x, _y, d) \
+    *(GLushort *)(buf + _x * 2 + _y * pitch) = d;
+
+#define READ_DEPTH(d, _x, _y) \
+    d = *(GLushort *)(buf + _x * 2 + _y * pitch);
+
+#define TAG(x) radeon##x##_16_untiled
+#include "depthtmp.h"
+
 /* 24 bit depth, 8 bit stencil depthbuffer functions
  */
 #define WRITE_DEPTH( _x, _y, d )					\
@@ -261,6 +271,16 @@
 #define TAG(x) radeon##x##_24_8
 #include "depthtmp.h"
 
+#define WRITE_DEPTH(_x, _y, d) do { \
+    GLuint tmp = *(buf + _x * 4 + _y * pitch); \
+    tmp &= 0xff000000; tmp |= ((d) & 0x00ffffff); \
+    *(GLuint *)(buf + _x * 4 + _y * pitch) = tmp; } while (0)
+#define READ_DEPTH(d, _x, _y) \
+    d = *(GLuint *)(buf + _x * 4 + _y * pitch) & 0x00ffffff;
+
+#define TAG(x) radeon##x##_24_8_untiled
+#include "depthtmp.h"
+
 
 /* ================================================================
  * Stencil buffer
@@ -288,6 +308,15 @@
 #define TAG(x) radeon##x##_24_8
 #include "stenciltmp.h"
 
+#define WRITE_STENCIL(_x, _y, d) do { \
+    GLuint tmp = *(buf + _x * 4 + _y * pitch); \
+    tmp &= 0x00ffffff; tmp |= (((d) & 0xff) << 24); \
+    *(GLuint *)(buf + _x * 4 + _y * pitch) = tmp; } while (0)
+#define READ_STENCIL(d, _x, _y) \
+    d = (*(GLuint *)(buf + _x * 4 + _y * pitch) & 0xff000000) >> 24;
+
+#define TAG(x) radeon##x##_24_8_untiled
+#include "stenciltmp.h"
 
 /*
  * This function is called to specify which buffer to read and write
@@ -354,10 +383,15 @@
    UNLOCK_HARDWARE( rmesa );
 }
 
+/* workaround, rv100 doesn't have a tiled depth buffer */
+
+#define PCI_CHIP_RADEON_LY      0x4C59
 void radeonInitSpanFuncs( GLcontext *ctx )
 {
    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
    struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
+   RADEONDRIPtr dri_priv =
+       (RADEONDRIPtr)rmesa->radeonScreen->driScreen->pDevPriv;
 
    swdd->SetBuffer = radeonSetBuffer;
 
@@ -388,22 +422,41 @@
 
    switch ( rmesa->glCtx->Visual.depthBits ) {
    case 16:
-      swdd->ReadDepthSpan	= radeonReadDepthSpan_16;
-      swdd->WriteDepthSpan	= radeonWriteDepthSpan_16;
-      swdd->ReadDepthPixels	= radeonReadDepthPixels_16;
-      swdd->WriteDepthPixels	= radeonWriteDepthPixels_16;
+      if (dri_priv->deviceID == PCI_CHIP_RADEON_LY) {
+         swdd->ReadDepthSpan       = radeonReadDepthSpan_16_untiled;
+         swdd->WriteDepthSpan      = radeonWriteDepthSpan_16_untiled;
+         swdd->ReadDepthPixels     = radeonReadDepthPixels_16_untiled;
+         swdd->WriteDepthPixels    = radeonWriteDepthPixels_16_untiled;
+      } else {
+         swdd->ReadDepthSpan	   = radeonReadDepthSpan_16;
+         swdd->WriteDepthSpan	   = radeonWriteDepthSpan_16;
+         swdd->ReadDepthPixels	   = radeonReadDepthPixels_16;
+         swdd->WriteDepthPixels	   = radeonWriteDepthPixels_16;
+      }
       break;
 
    case 24:
-      swdd->ReadDepthSpan	= radeonReadDepthSpan_24_8;
-      swdd->WriteDepthSpan	= radeonWriteDepthSpan_24_8;
-      swdd->ReadDepthPixels	= radeonReadDepthPixels_24_8;
-      swdd->WriteDepthPixels	= radeonWriteDepthPixels_24_8;
-
-      swdd->ReadStencilSpan	= radeonReadStencilSpan_24_8;
-      swdd->WriteStencilSpan	= radeonWriteStencilSpan_24_8;
-      swdd->ReadStencilPixels	= radeonReadStencilPixels_24_8;
-      swdd->WriteStencilPixels	= radeonWriteStencilPixels_24_8;
+      if (dri_priv->deviceID == PCI_CHIP_RADEON_LY) {
+         swdd->ReadDepthSpan	    = radeonReadDepthSpan_24_8_untiled;
+         swdd->WriteDepthSpan	    = radeonWriteDepthSpan_24_8_untiled;
+         swdd->ReadDepthPixels	    = radeonReadDepthPixels_24_8_untiled;
+         swdd->WriteDepthPixels	    = radeonWriteDepthPixels_24_8_untiled;
+
+         swdd->ReadStencilSpan	    = radeonReadStencilSpan_24_8_untiled;
+         swdd->WriteStencilSpan	    = radeonWriteStencilSpan_24_8_untiled;
+         swdd->ReadStencilPixels    = radeonReadStencilPixels_24_8_untiled;
+         swdd->WriteStencilPixels   = radeonWriteStencilPixels_24_8_untiled;
+      } else {
+         swdd->ReadDepthSpan	    = radeonReadDepthSpan_24_8;
+         swdd->WriteDepthSpan	    = radeonWriteDepthSpan_24_8;
+         swdd->ReadDepthPixels	    = radeonReadDepthPixels_24_8;
+         swdd->WriteDepthPixels	    = radeonWriteDepthPixels_24_8;
+
+         swdd->ReadStencilSpan	    = radeonReadStencilSpan_24_8;
+         swdd->WriteStencilSpan     = radeonWriteStencilSpan_24_8;
+         swdd->ReadStencilPixels    = radeonReadStencilPixels_24_8;
+         swdd->WriteStencilPixels   = radeonWriteStencilPixels_24_8;
+      }
       break;
 
    default:
